Timing·Bench — FPGA Timing Closure, STA & CDC

01 of 08A timing path is a race between data and a clock edge.

The launch register emits data after Tcq. Logic and routing consume the rest of the cycle. The capture register still needs setup time before the next edge. What remains is setup slack.

Launch, logic, route, capture

Block width is proportional to delay

Period

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Arrival

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Required

—

Setup slack

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The dashed capture marker is the latest legal arrival time, not the raw clock period. The hatched band between them is what setup time and uncertainty take away.

Path parameters

Met

Clock frequency

Tcq

Logic delay

Routing delay

Setup time

Clock uncertainty

Capture − launch skew

Try a scenario

setup slack = Tclk + skew − Tsetup − unc − (Tcq + logic + route)

02 of 08Setup and hold look at opposite sides of the same edge.

Setup asks whether the new data arrives early enough. Hold asks whether the old data stays long enough. Positive clock skew helps setup and hurts hold — exactly the trade visible below.

The circuit being checked

Values follow the sliders

Edge microscope

Skew and max-path delays come from the Path tab

Setup slack

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Hold slack

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Max fclk

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Critical check

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Hatched regions are the setup and hold exclusion windows around capture edges. The dot on each data trace marks its transition.

Inside the capture flip-flop

D must not move inside the hatched window

Minimum-delay path

Tcq min

Data min delay

Hold time

Hold uncertainty

hold slack = Tcq(min) + data(min) − skew − Thold − unc

STA does not simulate vectors

It propagates earliest and latest arrival times through timing arcs and checks every constrained path, including paths your testbench never toggles.

Max path ≠ min path

Setup uses the slow, latest data path. Hold uses the fast, earliest one. Fixing one can damage the other.

03 of 08Timing closure is a budget allocation problem, not “make logic faster.”

Pipeline depth, placement, fanout and routing all move the critical-path distribution. This toy placer is deliberately simplified, but it preserves the engineering direction of each knob.

Slack distribution, 64 paths

Toy place-and-route model

WNS

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TNS

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Failing paths

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Added latency

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Bars left of zero fail. The worst path is WNS; the sum of all negative slack is TNS.

Closure controls

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Pipeline cuts

Placement effort

Fanout pressure

Congestion

Apply a fix

What each fix actually attacks

Symptom	Likely dominant delay	Useful fixes	Common bad fix
Many levels of LUT/carry logic	Cell / logic	Pipeline, retime, restructure arithmetic, infer DSP/BRAM correctly	Cranking placer effort without changing architecture
Few levels, huge net delay	Routing / placement	Floorplan, reduce fanout, replicate drivers, colocate producer and consumer	Adding a random register far from the real bottleneck
One control net dominates hundreds of paths	Fanout + route	Register replication, local enables, hierarchy-aware placement	Buffering in RTL and assuming synthesis preserves it
Hold violations after setup optimization	Minimum path / skew	Dedicated hold fixing, route detours, delay cells where supported	Lowering the clock frequency — hold is same-edge and usually does not care

04 of 08Useful skew moves the edge. Retiming moves the register.

When one pipeline stage is long and the next is short, the short stage wastes most of its cycle. Delaying the middle register's clock, or moving logic across it, rebalances the two stages without adding latency.

Two-stage pipeline, FF1 in the middle

Tcq 0.25, tSU 0.15, tH 0.10 ns

Stage A setup

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Stage B setup

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Worst hold

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Fmax

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Top: the circuit, with block widths proportional to delay and any retimed logic hatched. Bottom: each stage's data against its capture edge. Useful skew slides FF1's edge; stage A gains exactly what stage B loses.

Pipeline

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Clock frequency

Shortest path

Stage A logic

Stage B logic

Useful skew on FF1 clock

Retiming: logic moved from A to B

Rebalance

A: T + skew − tSU − (Tcq + A − moved)
B: T − skew − tSU − (Tcq + B + moved)

Useful skew or retiming?

	Useful skew	Retiming
What moves	The clock edge at the middle register	The register itself, across combinational logic
Latency	Unchanged	Unchanged: registers are moved, not added
Hold cost	Delaying FF1's clock eats hold margin on paths into FF1 and adds it on paths out of FF1	Depends on the new shortest paths; usually small
In an FPGA	Limited. The clock network is prebuilt, so skew mostly comes from what place-and-route and clock optimization can adjust	Common. Synthesis (for example Vivado `synth_design -retiming`) and physical optimization can move registers
What blocks it	Hold violations on the short side, and limits of the clock tree	Registers with resets, enables, initial values, keep/DONT_TOUCH attributes, or loads the tool cannot duplicate

05 of 08One netlist has many timing realities.

Process, voltage and temperature change cell and interconnect delays. STA closes against timing corners, not a single “typical” delay. The plot uses an illustrative scaling model, not a vendor timing database.

Setup slack across temperature

Illustrative model

The solid line is the selected corner. Faint lines show the other process corners at the same voltage.

Corner

Process

Voltage

Temperature

Logic + route

—

Slack

—

Corner

—

Check

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Real FPGA timing is table- and model-driven and may not vary monotonically with every parameter. Use this to learn why multi-corner STA exists; use the vendor timing engine for signoff.

06 of 08A CDC problem is not a slow timing path.

Between unrelated clocks there is no stable phase relationship for STA to prove. The goal changes: contain metastability, preserve events, and keep multi-bit values coherent.

Asynchronous sample microscope

Probabilistic, not deterministic

Move the source phase until its transition lands near a destination edge. Stage 1 can go metastable; later stages buy resolution time before the signal is used.

Synchronizer

Destination clock

Source toggle rate

Synchronizer flops

Source phase

Metastability τ

Device constant C 1 ns

Resolution

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log₁₀ MTBF, yr

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Edge distance

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Risk

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MTBF ≈ exp(T_res / τ) / (C · f_clk · f_data)

τ and C here are illustrative teaching values. Real constants come from the FPGA vendor's device characterization. The lesson is the exponential dependence on resolution time.

07 of 08The right CDC circuit depends on what “information” means.

A 2‑FF synchronizer solves one persistent level. It does not automatically solve pulses, words, counters or streams. Pick the payload and the topology changes.

Crossing topology

Clock A on the left, clock B on the right

What are you crossing?

Why “synchronize every bit” fails

If an 8-bit bus changes from 0x7F → 0x80, independent bit synchronizers can resolve on different destination cycles. The receiver may briefly observe a word that never existed at the source.

For a coherent word, hold the data stable and synchronize a request/acknowledge handshake, or move the stream through an asynchronous FIFO whose pointers cross safely.

08 of 08STA is only as correct as the timing graph you describe.

Clocks, generated clocks, IO delays and exceptions define which races are real. An unconstrained path is not a passing path; it is a path your analysis may not be checking.

Pick a constraint, see what it does

SDC / XDC

Clocks

I/O

Exceptions

Clock relationships and modes

Exception danger meter

How broad is your exception?

SummaryThe short version.

The mental checklist to run before blaming the FPGA tool.

Timing and STA

Setup is the latest path: Data must arrive before the next capture edge, minus setup and uncertainty.
Hold is the earliest path: Data must not change too soon after the current capture edge. Lowering fclk normally does not fix hold.
Slack is the currency: Positive means margin. WNS is the worst failing path. TNS tells you whether the problem is isolated or systemic.
Read the path composition: Logic-dominated paths want architecture changes. Route-dominated paths want placement, fanout and floorplanning attention.

Clock-domain crossing

One stable bit: Use a 2+ stage synchronizer and mark it so implementation and CDC tools recognize the structure.
Pulse or event: Use pulse stretching, a toggle synchronizer or a handshake so the destination cannot miss a narrow event.
Word or stream: Use a handshake for occasional coherent words; use an async FIFO for sustained streaming data.
Pointer or count: Gray coding limits adjacent counts to one changing bit, which is why async FIFO pointers are usually Gray encoded.