FPGA and ASIC design, from RTL and verification through implementation and system bring-up. I work across SystemVerilog, VHDL, Vivado, Quartus and Cadence flows, with hardware experience in optical and wireless communications and post-quantum acceleration.
Digital hardware engineer with ten years in the communications industry, across hardware team leadership in Abu Dhabi, backscatter ASIC design lead in Canada, and semiconductor bring-up and verification in Brazil. At the Technology Innovation Institute I lead the digital design of a free-space optical communication system — coordinating PCB, FPGA firmware, analog front-end, and system integration — and own the pointing, acquisition and tracking subsystem end to end. I also built the laboratory validation platform that correlates Vivado simulation, ILA captures, oscilloscope data, BER measurements, link-budget estimates and live instrument telemetry into a single workflow. Previously I led the team that delivered a post-quantum cryptography hardware accelerator reaching 162x over a single-core software baseline, and before that designed the digital architecture of the BSC2000 backscatter ASIC and invented the frame-check-sequence preservation method behind two granted US patents.
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Study
2016– 2018CEITEC S.A. — Porto Alegre, Brazil
Bring-up team, then EDA team
Validated the very-high-bit-rate contactless interface of the Brazilian passport chip against ISO 14443-4, then moved to the EDA team to automate the design flow.
stackISO 14443-4, ISO 7816-4; OrCAD; C++ with Qt; uC/OS; RedHat, Python, Bash, DesignSync
Wrote tests validating the VHBR feature of ISO 14443-4 for the Brazilian passport contactless interface.
Wrote C++ peripheral communication using Qt, and added methods to an embedded processor running uC/OS.
On the EDA team: RedHat system administration, Python and Bash automation, and an improved role system for DesignSync.
ISO 14443-4 exchange between reader and passport chip. Move the rate slider: the PPS negotiation and SELECT round-trip speed up as the bit rate climbs into the very-high-bit-rate range.
2018– 2020Datacom — Porto Alegre, Brazil
Developer — Hardware and Software R&D
Built a 40 Gbit/s IEEE 802.3ba test switch on Virtex-7 with built-in self-test and RFC 2544 validation, and cut the area of the legacy architecture by 93%.
stackVirtex-7; VHDL, Verilog; 802.3ba; PCIe; VXLAN, EVPN, BGP, GRE, GENEVE; C raw sockets; C#
Developed a 40 Gbit/s test switch targeting Virtex-7, implementing IEEE 802.3ba with a built-in self-test architecture and an RFC 2544 validation module.
Cut area consumed by legacy architectures by 93% through critical-path and area analysis.
Created PCIe communication modules between FPGA and host, and in-FPGA layer 2 and layer 3 traffic generators.
Implemented VXLAN, EVPN, BGP, GRE and GENEVE inside equipment; used C raw sockets for layer-2 communication.
The 40 Gbit/s test switch. Frame size and load drive the lane utilisation; toggle the legacy architecture to compare area, and run RFC 2544 to see the built-in self-test.
C# test application driving Linux virtual firmware instances. Normal traffic uses the primary route; failure mode moves it to the backup path.
2020– 2022HaiLa Technologies — Montreal, Canada
Lead Digital Hardware Engineer
Designed the digital architecture of BSC2000, an ultra-low-power Wi-Fi backscatter ASIC, and invented the frame-check-sequence preservation method that became two granted US patents.
stackASIC RTL in SystemVerilog; UVM, SVA; SPI, APB; RISC-V firmware; 802.11, GNU Radio; Python host stack
Designed the digital architecture of BSC2000, an ultra-low-power backscatter ASIC operating in the Wi-Fi band, and BSC1000, its FPGA demo unit.
Discovered and implemented a novel approach to 802.11 FCS manipulation — two granted US patents.
Created a communication protocol over 802.11 with an error-detection technique protecting it, and an encoding architecture transmitting data on top of pre-existing layer-2 infrastructure.
Verified the ASIC with UVM and SVA; implemented SPI and APB modules; wrote firmware for a RISC-V microprocessor.
Explored channel coding to protect injected data, and singulation of unknown devices in radiated media. Tested RF environments with GNU Radio.
Ultra-low-power Wi-Fi backscatter. The tag has no transmitter. It reflects the chosen AP's own frame — a tag bit of 1 flips the phase — and radiates the reply in every direction. Only the AP whose frame it rode lights its RX LED.
2022– nowTechnology Innovation Institute — Abu Dhabi, UAE
Lead Hardware Engineer
Led the team that delivered a post-quantum key-encapsulation hardware accelerator at 162× a single-core software baseline, owning the hardware and software architecture and the verification plan.
Led a team of engineers delivering a high-throughput hardware encryptor for post-quantum key encapsulation, owning hardware and software architecture and the verification plan.
Accelerator module reached 162x over the single-core software baseline.
Built a hardware authenticator combining Kyber key encapsulation, Dilithium signatures and FIDO2.
Integrated PCIe Gen4 x16 and DDR4 into the architecture.
Implemented a ring-oscillator TRNG and a novel method for unbiased generation.
Created a Python framework unifying tool flows across Xcelium, Vivado, Questa, Quartus, Libero, Genus and Verilator.
Developed BFMs for AXI4, Avalon-MM/ST and APB with generic and randomised packet generation.
Used SystemVerilog VPI and DPI to bridge UVM classes and C functions; added coverage analysis and SVA properties.
Designed abstraction modules hiding multiple memory hierarchies, and synchronisation for high-throughput serialisation.
Introduced CI/CD pipelines into the project flow; ran price and availability analysis across the full BOM.
The KEM and signature datapath. Drag the card into the x16 slot and the queue drains through six KEM units at 162×; pull it out and the CPU takes the same work at 1×.
The hardware authenticator. Drag the key into the USB port, then step through the challenge. The FPGA hashes and signs inside the device; the secret key is generated there and never leaves.
2026– nowTechnology Innovation Institute — Abu Dhabi, UAE
Lead Digital Design Engineer — Wireless Communications
Took a free-space optical video link from concept to a working proof of concept over a 1 km horizontal path, and own the pointing, acquisition and tracking that keeps it up under turbulence.
stackXilinx ZynqMP on ZCU102; Vivado, Vitis; SystemVerilog; Python lab automation; link budget, BER
Developed a proof-of-concept free-space optical communication system for high-throughput, low-latency video transmission.
Own the complete pointing, acquisition and tracking solution for reliable optical-link establishment and stabilisation.
Coordinate PCB, FPGA firmware, analog front-end, system bring-up and hardware integration across the programme.
Designed the laboratory validation platform that correlates Vivado simulations, ILA captures, oscilloscope measurements, BER results, link-budget estimates and real-time bench telemetry.
Xilinx ZynqMP on ZCU102, Vivado and Vitis flows.
HDMI over a laser: two ZynqMP terminals, 1 km of turbulent air, and the tracking loop that keeps the picture up. The left FPGA serialises an HDMI stream onto the beam; the right one recovers it through FEC and drives a monitor. The quad detector reads where the spot landed and the fast steering mirror closes the loop. Raise the turbulence and the picture breaks into blocks before the link drops; open the loop or kick the beam and watch it reacquire.
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Engineering skills
Select a skill to see its animation alongside. Hover for where it was used.
The tag changes the payload; the original FCS stays. Switch preservation off to see the difference.how the method works
A backscattering tag has no transmitter; it reflects a frame another radio is already sending. That frame’s check sequence was computed by an access point that knows nothing about the tag, so any changed bit makes every receiver drop it. The method: the access point ends its payload with a run of zeros, the tag overwrites the start of that run with its data and then a short preservation sequence — the XOR of the CRC of the tag data and the CRC of as many zeros, serialized in the required bit order (least-significant byte first in this reflected CRC-32 implementation) — and the original FCS stays correct. Below, live, with a real CRC-32.
Courses
courses by
Inside the portfolio
A career on an AXI bus. Run the trace, then inspect each transaction.
Ready · recorded SV simulation
Write 0x0000 · hire recordRead base + 0x00 · hiring date / tenurebase + 0x08 · position / locationbase + 0x10 · skills burst
—C1 —M1 —Δ —
TOP.career_top▸ click a folded channel to open its signals · click to place C1 · shift-click for M1 · ←→ move · n/p step transactions · click a company segment to open that role
Career history
From
To
Employer
Role
Location
Run plays the recorded SystemVerilog trace once. Each hire briefly holds the timeline; afterwards, pan, zoom and inspect the decoded bus values.