Optical link demonstrated
Pointing, acquisition and tracking owned end to end for a free-space optical system.
Matheus Ferronato
I design digital hardware for wireless communications, data acceleration and low-power devices, with experience in high-throughput data transfer, wired and wireless networking, power-efficient architectures and space applications.
Lead Digital Design Engineer
Technology Innovation Institute
Pointing, acquisition and tracking owned end to end for a free-space optical system.
Led the team delivering a hardware accelerator versus a single-core software baseline.
Designed digital ASIC architectures for ultra-low-power backscatter communication and protocol processing.
Granted patents covering frame-check-sequence preservation for backscatter communication systems.
Interactive labs covering FPGA timing, digital interfaces, DSP, signal integrity, RF and measurement fundamentals. Run directly in your browser.
FPGA / ASIC
Explore setup and hold timing, slack, clock skew, timing closure, metastability and clock-domain crossing.
Open the FPGA timing lab ↗Signal integrity
Explore transmission lines, reflections, differential-pair skew, crosstalk, controlled impedance and return paths.
Open the signal-integrity lab ↗DSP
Compare FIR and IIR filters, DFT and FFT behavior, frequency response, sampling and time-domain effects.
Open the DSP lab ↗Digital interfaces
Inspect transactions cycle by cycle and explore timing and handshakes across common digital bus protocols.
Open the protocol lab ↗RF engineering
Visualize complex impedance, reflection coefficient, matching behavior and movement across the Smith chart.
Open the RF lab ↗Measurement
Explore bandwidth, sample rate, Nyquist limits, aliasing, filtering and waveform reconstruction.
Open the oscilloscope lab ↗