ferronato.me

Matheus Ferronato

FPGA & ASIC engineer.
From RTL to
working systems.

I design digital hardware for wireless communications, data acceleration and low-power devices, with experience in high-throughput data transfer, wired and wireless networking, power-efficient architectures and space applications.

Lead Digital Design Engineer
Technology Innovation Institute

1 km

Optical link demonstrated

Pointing, acquisition and tracking owned end to end for a free-space optical system.

162×

Post-quantum acceleration

Led the team delivering a hardware accelerator versus a single-core software baseline.

ASIC

Backscatter silicon design

Designed digital ASIC architectures for ultra-low-power backscatter communication and protocol processing.

2 US patents

Backscatter innovation

Granted patents covering frame-check-sequence preservation for backscatter communication systems.

  • FPGA / ASIC
  • Verilog / SystemVerilog
  • VHDL
  • UVM / SVA
  • Vivado / Quartus
  • PCIe / Ethernet
  • AXI / DDR4
  • Python / Tcl

Explore the engineering

All interactive labs ↗

Interactive labs covering FPGA timing, digital interfaces, DSP, signal integrity, RF and measurement fundamentals. Run directly in your browser.

Let’s talk

matheus@ferronato.me