APB
driven by the manager driven by the subordinate edge where the transfer is captured undriven or don't care
Cycle 1 of 4
| Signal | Value | Driven by |
|---|
Timing model scope
One illustrative transaction per trace. Avalon-ST uses readyLatency = 0; Avalon-MM uses waitrequestAllowance = 0. SPI bit values are summarized per full clock period; sampling markers identify the correct edge, without a half-cycle launch simulation. I2C high means release to a pull-up. AXI WRAP lengths in the explorer snap to 2, 4 or 8; use the burst lab for 16 beats.
Where it fits
Compare interfaces
Pick up to four. The rows are the properties that change what you have to write in RTL, not the ones that look good on a datasheet.
Reference
The handful of ideas that all ten of these interfaces are assembled from.
- Valid and ready
- A transfer happens on a clock edge where both are high. The sender may not withdraw valid once it is asserted, and the receiver may drop ready whenever it likes. Deriving valid from ready is the standard way to build a deadlock, because both ends end up waiting for the other.
- Request and wait
- The manager asserts a request and holds every associated signal steady until the subordinate stops saying wait. APB's PREADY, AHB's HREADY, Avalon's waitrequest and Wishbone's ACK are the same idea with different polarity and different names.
- Pipelining versus channels
- AHB-Lite overlaps one address phase with one data phase, which is cheap and keeps everything in order. AXI goes further and makes address, data and response fully independent, which buys throughput and costs you the simple global ordering; AXI still defines ordering requirements, including per-ID rules.
- Bursts
- One address describes several beats, so the address phase stops being the bottleneck. AXI4 encodes length, size and type; AXI4-Lite deliberately has none of it; a stream does not need it because it never had an address to amortise.
- Outstanding transactions
- Issuing a second request before the first has answered. It allows throughput to cover memory latency, and the moment you allow it you have to decide what may complete out of order. That is what AXI IDs are for.
- Who drives the wire
- Push-pull buses have exactly one driver per net and the direction is fixed at elaboration. I2C shares one wire between every device using open drain, so the interesting question on every cycle is which end is pulling it low, and the diagrams here colour it accordingly.
AXI burst attributes, read together
- AxLEN[7:0]
- Beats minus one. 0 is a single beat, 3 is four beats, 255 is the 256-beat maximum for INCR.
- AxSIZE[2:0]
- Bytes per beat, as a power of two. 2 means four bytes, so a four-beat INCR burst covers sixteen bytes.
- AxBURST[1:0]
- How the address moves between beats. FIXED stays put, INCR advances, WRAP advances and rolls back to the start of an aligned block, which is how a cache line fill returns the critical word first.
Set a read burst to WRAP in the explorer and watch the address sequence in the caption roll over rather than run past the block boundary.
Keyboard
- ←→step one cycle
- Spaceplay or pause
- HomeEndfirst or last cycle